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ARIZONA MICROTEK, INC.
AZ12000, AZ12001
Phase-Locked Loop Clock Generator FEATURES
* * * * * * * * *
PECL (AZ12000) or LVDS (AZ12001) Outputs Operating Range 3.0V to 5.5V Internal Crystal Oscillator Driver Internal Edge-Matching Phase/Frequency Detector Internal Charge-Pump and Integrator Amplifier Internal or External VCO Divide by 4, 8, 16, 32 RF Bipolar Design for Low Phase Noise Available in a 4x4mm MLP Package PACKAGE
MLP 24 (4x4) MLP 24 (4x4) DIE DIE
1 2 3
PACKAGE AVAILABILITY PART NO.
AZ12000K AZ12001K AZ12000XP AZ12001XP
MARKING
AZ12000 AZ12001 N/A N/A
NOTES
1,2 1,2 3 3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: "YY" for year followed by "WW" for week. Waffle Pack
DESCRIPTION
The AZ12000/AZ12001 contains all of the functional elements necessary to implement a Phase-Locked Loop for clock multiplication at frequencies up to 800 MHz. A reference crystal oscillator driver operates at frequencies up to 200 MHz providing support for 4 times multiplication. The dynamic properties of the PLL are under the control of the user through selection of the desired external components. BLOCK DIAGRAM
T UOT NI Q T UPT UO O CV Q LESO CV XUM XUM
REFFUB O CV
1630 S. STAPLEY DR., SUITE 127 * MESA, ARIZONA 85204 * USA * (480) 962-5881 * FAX (480) 890-2541 www.azmicrotek.com
ROT ARGET NI O CVTXE KN AT OCVTXE 23,61,8,4 YB EDIVID 1SD 2SD
PMUP EGRAHC TCE TED QERF /ESAHP
M UST NI FERT NI
T UOP C FERP C LOPPC RVRD TPT UO RV CR T UP NI
BBV
074
A m4
EE
V
NIFER
EEV CC V OCV V
BB
CC
T UOFER V
AZ12000 AZ12001
CCV CCV
Bottom Center pad may be left open or tied to VEE.
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol VCC VI IOUT TA TSTG Characteristic Power Supply (VEE = GND) Input Voltage (VEE = GND) -- Continuous ECL/PECL Output Current -- Surge Operating Temperature Range Storage Temperature Range Rating 0 to +6.0 0 to +6.0 40 80 -40 to +85 -65 to +150 Unit Vdc Vdc mA C C
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TUOTNI 31
LOPPC 41
EEV
BBV
Q Q
81 71 61 51
EEV MUSTNI FERTNI FERPC TUOPC NIFER 21 11 01 9 8 7
91
02
)weiV poT ,PLM niP 42( 10021ZA ,00021ZA :tuoniP
C/N LESOCV KNAT 12 22 32
CCVOCV
42 1 OCVTXE 2 OCVTXE 5 6 TUOFER 3 4 1SD 2SD
EEV
AZ12000 AZ12001
AZ12000 FUNCTIONAL PIN DESCRIPTIONS Pin No Pin Name Functional Description Reference Crystal Resonator Input This pin includes an on-chip 470 pull REFIN down resistor to VBB. The input from the resonator circuit should be AC coupled. Crystal Resonator Output Drive This pin is an inverted and amplified version of the signal on the REFIN pin. The gain from REFIN to REFOUT is REFOUT approximately 20. The IC includes a 4 ma on-chip current source. If more current is needed, the REFOUT pin may be connected to VEE through a resistor to provide up to 8 ma additional current. Charge Pump Reference Output The pin voltage is nominally 1.2 volts below CPREF VCC. If an external integrator is used, CPREF should be connected to the integrator reference input through a bias current cancellation network. Charge Pump Output The charge pump output voltage is V(CPREF) 0.3V during a phase correction pulse. When there is no correction pulse the output CPOUT goes high impedance. If an external integrator is used, CPOUT should be connected to the input integrator resistor. Charge Pump Polarity Logic LOW on this pin causes CPOUT to go low when the VCO frequency is too low, and go high when the VCO frequency is too high. Logic HIGH on this pin causes CPOUT to go low when the VCO CPPOL frequency is too high, and go high when the VCO frequency is too low. This pin should be LOW when the internal VCO is used. If this pin is left open it is pulled to the HIGH condition. Integrator Reference Input This pin should be connected to CPREF through a bias current cancellation network Integrator Summing Junction This pin is the summing junction for the integrator amplifier Integrator Output Internal/External VCO Select Logic HIGH on this pin enables the internal VCO. Logic LOW on this pin disables the internal VCO and allows use of the EXTVCO inputs. If this pin is left open it is pulled to the HIGH condition. VCO Tank The tank components connect between this pin and VCC. External VCO Input The external VCO input pins should be driven differentially for best performance. Divide Select VCO divide ratios are selected as shown: DS1 Ratio DS2 LOW LOW /4 LOW HIGH /8 HIGH LOW /16 HIGH HIGH /32 If the pins are left open they are pulled to the HIGH condition. Clock Output These pins are the main (multiplied) clock output. No Connect This pin is used during factory test. It mist be left open. Reference Voltage Output This pin is used to bias the REFIN signal. It must be bypassed externally to the VEE pins with a 0.01 F capacitor. Positive Supply +3.0 to +5.5 V for PECL mode, Ground for ECL mode. VCO Positive Supply +3.0 to +5.5 V for PECL mode, Ground for ECL mode. Negative Supply Ground for PECL mode, -3.0 to -5.5 V for ECL mode. Logic Level
ECL/PECL
CMOS/TTL compatible
INTREF INTSUM INTOUT
VCOSEL
CMOS/TTL compatible
TANK EXTVCO EXTVCO
ECL/PECL
DS2 DS1
CMOS/TTL compatible
Q Q N/C VBB VCC VCOVCC VEE
ECL/PECL
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AZ12000 AZ12001
AZ12001 FUNCTIONAL PIN DESCRIPTIONS Pin No Pin Name Functional Description Reference Crystal Resonator Input This pin includes an on-chip 470 pull REFIN down resistor to VBB. The input from the resonator circuit should be AC coupled. Crystal Resonator Output Drive This pin is an inverted and amplified version of the signal on the REFIN pin. The gain from REFIN to REFOUT is REFOUT approximately 20. The IC includes a 4 ma on-chip current source. If more current is needed, the REFOUT pin may be connected to VEE through a resistor to provide up to 8 ma additional current. Charge Pump Reference Output The pin voltage is nominally 1.2 volts below CPREF VCC. If an external integrator is used, CPREF should be connected to the integrator reference input through a bias current cancellation network. Charge Pump Output The charge pump output voltage is V(CPREF) 0.3V during a phase correction pulse. When there is no correction pulse the output CPOUT goes high impedance. If an external integrator is used, CPOUT should be connected to the input integrator resistor. Charge Pump Polarity Logic LOW on this pin causes CPOUT to go low when the VCO frequency is too low, and go high when the VCO frequency is too high. Logic HIGH on this pin causes CPOUT to go low when the VCO CPPOL frequency is too high, and go high when the VCO frequency is too low. This pin should be LOW when the internal VCO is used. If this pin is left open it is pulled to the HIGH condition. Integrator Reference Input This pin should be connected to CPREF through a bias current cancellation network Integrator Summing Junction This pin is the summing junction for the integrator amplifier Integrator Output Internal/External VCO Select Logic HIGH on this pin enables the internal VCO. Logic LOW on this pin disables the internal VCO and allows use of the EXTVCO inputs. If this pin is left open it is pulled to the HIGH condition. VCO Tank The tank components connect between this pin and VCC. External VCO Input The external VCO input pins should be driven differentially for best performance. Divide Select VCO divide ratios are selected as shown: DS1 Ratio DS2 LOW LOW /4 LOW HIGH /8 HIGH LOW /16 HIGH HIGH /32 If the pins are left open they are pulled to the HIGH condition. Clock Output These pins are the main (multiplied) clock output. No Connect This pin is used during factory test. It must be left open. Reference Voltage Output This pin is used to bias the REFIN signal. It must be bypassed externally to the VEE pins with a 0.01 F capacitor. Positive Supply +3.0 to +5.5 V VCO Positive Supply +3.0 to +5.5 V Negative Supply Ground Logic Level
PECL
CMOS/TTL compatible
INTREF INTSUM INTOUT
VCOSEL
CMOS/TTL compatible
TANK EXTVCO EXTVCO
PECL
DS2 DS1
CMOS/TTL Compatible
Q Q N/C VBB VCC VCOVCC VEE
LVDS
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AZ12000 AZ12001
AZ12000 (PECL OUTPUT) DC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol VBB RPD ICS VHCTL VLCTL VOH Output LOW Voltage1 VOL Q Q Characteristic Reference Voltage REFIN Pull-Down resistor to VBB REFOUT Current Source High level integrator output Low level integrator output Output HIGH Voltage
1
-40C Min Max VCC VCC -1.38 -1.26
0C Min Max VCC VCC -1.38 -1.26
Min VCC -1.38
25C Typ VCC -1.31 470 4.0
85C Max VCC -1.26 Min VCC -1.38 Max VCC -1.26
Unit V ma V
VCC -1.0 VEE +0.5 VCC -1085 VCC -1830 VCC -1165 VCC -880 VCC -1555 VCC -880 VCC -1025 VCC -1810 VCC -1165 VCC -880 VCC -1620 VCC -880 VCC -1025 VCC -1810 VCC -1165 VCC -955 VCC -1705 VCC -880 VCC -1620 VCC -880 VCC -1025 VCC -1810 VCC -1165 VCC -880 VCC -1620 VCC -880
V mV
Q Q
mV
Input HIGH Voltage, PECL/ECL VIH EXTVCO EXTVCO Input LOW Voltage, PECL/ECL VIL EXTVCO EXTVCO Input HIGH Voltage, TTL/CMOS CPPOL VIH VCOSEL DS2 DS1 Input HIGH Voltage, TTL/CMOS CPPOL VIL VCOSEL DS2 DS1 ICC (IEE) Power Supply Current 1. Load is 50 to VCC-2V
mV
VCC -1810
VCC -1475
VCC -1810
VCC -1475
VCC -1810
VCC -1475
VCC -1810
VCC -1475
mV
VEE +2.0
VEE +2.0
VEE +2.0
VEE +2.0
V
VEE +0.8
VEE +0.8
VEE +0.8
VEE +0.8
V
55
58
45
58
60
mA
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AZ12000 AZ12001
AZ12001 (LVDS OUTPUT) DC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol VBB RPD ICS VHCTL VLCTL VOH Output LOW Voltage1 VOL Q Q VCC -1165 VCC -880 VCC -1165 VCC -880 VCC -1165 VCC -880 VCC -1165 VCC -880 mV Characteristic Reference Voltage REFIN Pull-Down resistor to VBB REFOUT Current Source High level integrator output Low level integrator output Output HIGH Voltage
1
-40C Min Max VCC VCC -1.38 -1.26
0C Min Max VCC VCC -1.38 -1.26
Min VCC -1.38
25C Typ VCC -1.31 470 4.0
85C Max VCC -1.26 Min VCC -1.38 Max VCC -1.26
Unit V ma V
VCC -1.0 VEE +0.5
V mV
Q Q
Input HIGH Voltage, PECL/ECL VIH EXTVCO EXTVCO Input LOW Voltage, PECL/ECL VIL EXTVCO EXTVCO Input HIGH Voltage, TTL/CMOS CPPOL VIH VCOSEL DS2 DS1 Input HIGH Voltage, TTL/CMOS CPPOL VIL VCOSEL DS2 DS1 ICC (IEE) Power Supply Current 1. 100 between outputs
mV
VCC -1810
VCC -1475
VCC -1810
VCC -1475
VCC -1810
VCC -1475
VCC -1810
VCC -1475
mV
VEE +2.0
VEE +2.0
VEE +2.0
VEE +2.0
V
VEE +0.8
VEE +0.8
VEE +0.8
VEE +0.8
V
60
60
60
mA
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AZ12000 AZ12001
AZ 12000 (PECL OUTPUT) AC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol Characteristic Min -40C Typ Max Min 25C Typ Max Min 85C Typ Max Unit
AV1 ZO APD fVCO tr / tf
Gain, REFIN to REFOUT Output Impedance, REFOUT Phase Detector Gain VCO frequency (Internal or External) Output Rise & Fall Times (20% - 80%) Q Q
20 TBD 20.3 800
V/V radians/V MHz ps
120 120
AZ12001 (LVDS OUTPUT) AC CHARACTERISTICS (VCC = +3.0 to +5.5 V, VEE = GND)
Symbol Characteristic Min -40C Typ Max Min 25C Typ Max Min 85C Typ Max Unit
AV1 ZO APD fVCO tr / tf
Gain, REFIN to REFOUT Output Impedance, REFOUT Phase Detector Gain VCO frequency (Internal or External) Output Rise & Fall Times (20% - 80%) Q Q
20 TBD 20.3 800
V/V Radians/V MHz ps
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AZ12000 AZ12001
Internal Reference Oscillator The PLL reference can be generated either with an internal oscillator or with an external source. In either case, the input is the REFIN pin. This should be AC coupled since the input is internally biased to VBB. The REFOUT pin should be left open when an external reference is used. The exact topology of the crystal circuit will vary based on the resonant mode of the crystal. The circuit shown is for a series resonant crystal. The AC gain between the REFIN and REFOUT pins is approximately 20. This value is sufficient to overcome crystal matching network losses without phase noise degradation caused by an excessive drive level. An internal current source on REFOUT eliminates the need for an external load resistor.
L3
Y1
C3
Figure 1 Reference Oscillator
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BBV
BB
GROUND
074
C4
RVRD TPTUO RVCR TUPNI Am4
)DNUORG( EEV
TUOFER NIFER V
AZ12000 AZ12001
Loop Filter Design The combination of the phase detector, amplifier, VCO and divider form a second-order phase-locked loop. Proper selection of the loop components is important to obtain stable, low jitter operation. The loop bandwidth (or natural frequency, n) and damping factor () are the two major driving forces that define the loop's response to a disturbance. The value of is typically 0.7 to ensure the fastest step response consistent with no ringing. However in many oscillator application may be 3 or higher to provide further phase noise reduction. n is chosen as a compromise between settling time, VCO jitter and reference feedthrough. These values can be computed by the following equations:
n =
=
1 N
K KVCO
1
2 n
2
1 = R1C1 2 = R2C1
K = Phase Detector Gain (20.3 radians/V)
KVCO = VCO Gain (radians/sec/volt)
N = Frequency Divisor value (4,8, 16 or 32)
The component definitions are shown in the figure below. R3 should be equal to R1 to minimize integrator offsets.
EGATLOV LORTNOC OCV
C1
R1
R2
R3
Figure 2 Charge Pump and Integrator
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TUOTNI
ROTARGETNI PMUP EGRAHC
MUSTNI FERTNI
TUOPC FERPC
AZ12000 AZ12001
Internal VCO The internal VCO is designed for reliable, low jitter operation up to 800 MHz. It operates as a single terminal negative impedance type circuit. The tank circuit should have a minimum Q of 12 for reliable operation. The series combination of CV and C1 resonate with L1 to set the operating frequency. The VCO control voltage is isolated through an inductor or resistor and changes the varactor capacitance based on that control voltage. Note that the CPPOL pin should be tied high for internal VCO operation since the tank frequency decreases with increasing control voltage.
VCOVCC
VARACTOR
TANK
VCO CONTROL VOLTAGE
CV L2 L1 C2
R1
Figure 3 Internal VCO with Tank External VCO When VCOSEL is high, the internal VCO is disabled and the EXTVCO, EXTVCO pair is enabled. That input pair is sine wave and PECL compatible. The CPPOL pin sets the frequency slope polarity based on the operation of the external VCO. When CPPOL is low, the charge pump generates pulses for an integrator and loop filter assuming the VCO frequency goes lower as the integrator output voltage increases. When CPPOL is high, pulses are generated for a VCO in which the frequency goes higher as the integrator output voltage increases.
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KNAT OCV
AZ12000 AZ12001
Application Circuit A typical application circuit is shown in Figure 4. This drawing shows use of the internal reference oscillator and internal VCO.
VCC
VARACTOR
C1 CV L2 L1 R3 C2
TANK
R1
R2
C4
C3
C4 0.01 F
F
CONNECT TO VCC OR GROUND FOR REQUIRED DIVISION RATIO
GROUND
Figure 4. Typical Application with Crystal Reference and Internal VCO
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Q
Q
Y1
TUPTUO OCV
L3
KNAT
10021ZA 00021ZA
PECL OR LVDS OUTPUT
LESOCV
XUM XUM
TUOTNI
ROTARGETNI MUSTNI FERTNI
REFFUB OCV
OCVTXE OCVTXE
1SD
TUOPC FERPC LOPPC 23,61,8,4 YB EDIVID
PMUP EGRAHC TCETED QERF /ESAHP
2SD
RVRD TPTUO RVCR TUPNI
BBV
074
Am4
CCV ,CCVOCV EE
TUOFER NIFER
BB EE
V V V
AZ12000 AZ12001
PACKAGE DIAGRAM MLP 24
NOTES 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. 2. THE TERMINAL #1 AND PAD NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM PAD TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
DIM A A1 A3 b D D2 E E2 e L aaa bbb ccc
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.25 REF 0.18 0.30 3.90 4.10 2.65 2.95 3.90 4.10 2.65 2.95 0.50 BSC 0.35 0.45 0.25 0.10 0.10
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AZ12000 AZ12001
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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